TSMC’s Japan 3nm Fab Marks the End of Taiwan’s Foundry Monopoly
A $17 billion bet on geopolitical decoupling reshapes semiconductor sovereignty as allied nations fragment chip production.
TSMC will mass produce 3nm chips at its Kumamoto, Japan facility starting in 2028—a strategic reversal from its original plan to manufacture less advanced semiconductors that signals the semiconductor industry’s most significant supply chain realignment in decades.
The upgrade, formalized in a Taiwan government filing yesterday, increases TSMC’s Japan investment from $12.2 billion to $17 billion. The facility will produce 15,000 12-inch wafers monthly using the same 3nm process that powers Apple’s latest processors—technology previously confined to Taiwan’s Hsinchu heartland. TSMC Chairman C.C. Wei framed the move explicitly around AI infrastructure:
“We believe this fab will further contribute to the local economic growth and, most importantly, form a foundation for Japan’s AI business.”
— C.C. Wei, TSMC Chairman
The decision reflects a calculation that Taiwan concentration risk—TSMC controls 70% of global foundry revenue and over 90% of the world’s most advanced chip production, per LongYield—now outweighs the efficiency gains of centralised manufacturing. Cross-strait tensions have made diversification a strategic imperative for Western customers and TSMC alike, particularly as ScienceDirect analysis highlights Taiwan’s semiconductor supply chain vulnerability to quarantine scenarios before 2027.
Japan’s Industrial Policy Gambit
Japan’s government has mobilised ¥3.9 trillion ($25.5 billion) in semiconductor subsidies over three years through April 2024—equivalent to 0.71% of GDP, according to Columbia Business School research. For fiscal year 2026, which began this week, the industry ministry quadrupled its semiconductor and AI budget to ¥1.23 trillion ($7.9 billion), as reported by Japan Times.
The scale reflects strategic autonomy ambitions that extend beyond TSMC. Japan’s domestic champion Rapidus has received ¥920 billion cumulatively, with an additional ¥150 billion earmarked for the current fiscal year to develop 2nm production capabilities by 2027. The government targets ¥15 trillion in annual semiconductor sales by 2030, a figure that requires capturing meaningful share of advanced-node production currently monopolised by Taiwan and South Korea.
The Capex Arms Race
TSMC’s Japan commitment arrives amid unprecedented global semiconductor capital spending. Industry-wide capex is projected to reach $200 billion in 2026, up 20% year-over-year, with TSMC guiding $52-56 billion (a 27-37% increase from 2025) and Samsung deploying 110 trillion won ($73 billion), per Electronics Weekly.
| Company | 2026 Capex | YoY Change | Strategic Focus |
|---|---|---|---|
| Samsung | $73B | +20% | 2nm mass production, HBM4, Texas fab |
| TSMC | $52-56B | +27-37% | Japan 3nm, Arizona expansion |
| Intel | ~$25B (est.) | Stable | Arizona, Ohio fabs |
Samsung began 2nm gate-all-around (GAA) mass production in Q4 2025, ahead of both Intel and TSMC in volume manufacturing, according to Anysilicon. The company is also planning a $170 million chip packaging R&D center in Yokohama, scheduled to open in March 2027. Stacy Rasgon, senior semiconductor analyst at Bernstein Research, called Samsung’s spending “unprecedented for a single company in a single year.”
The competitive dynamic has shifted from pure process leadership to geographic diversification. Intel’s Arizona and Ohio fabs, Samsung’s Texas facility coming online in 2026, and TSMC’s dual Arizona and Japan operations represent active fragmentation of the Western bloc’s foundry footprint—a reversal of the cost-optimised concentration that defined the industry for three decades.
China’s Parallel Decoupling
Japan’s semiconductor renaissance unfolds against China’s stalled self-sufficiency campaign. Despite government directives and import substitution pressure, China’s semiconductor self-sufficiency rate rose from just 5% in 2018 to 12% in 2023—far below the 70% target set in the Made in China 2025 industrial plan, per Ainvest analysis.
Western export controls have prevented Chinese foundries from accessing extreme ultraviolet (EUV) lithography systems required for sub-7nm production. TSMC’s Japan 3nm fab will use the same ASML EUV tools that remain embargoed for mainland Chinese buyers, cementing a technology gap that now carries explicit geopolitical intent.
The result is a bifurcated semiconductor world: China pursuing trailing-edge volume manufacturing while the US, Japan, South Korea, and Taiwan coordinate advanced-node production within allied geographies. TSMC’s Japan fab serves both commercial and strategic objectives—reducing Taiwan exposure while maintaining Western technology leadership against Chinese alternatives.
What to Watch
TSMC’s 2028 production timeline for Japan 3nm chips creates a three-year window where Taiwan remains the sole source for the most advanced Semiconductors. Any escalation in cross-strait tensions during this period would stress Western Supply Chains before geographic diversification provides meaningful redundancy.
Samsung’s 2nm production ramp and Intel’s foundry turnaround efforts will determine whether TSMC faces genuine competition in allied markets or retains de facto monopoly pricing power even with dispersed manufacturing. Japan’s Rapidus 2nm timeline—currently targeting 2027—remains unproven at commercial scale.
China’s response merits close monitoring. If import substitution continues to stall below 15% self-sufficiency, Beijing may intensify semiconductor equipment indigenisation or accelerate SMIC’s mature-node capacity expansion to capture segments where Western export controls are less restrictive. The capex arms race extends beyond allied nations—it represents a redrawing of global technology sovereignty with semiconductor manufacturing as the primary battlefield.